Integrated circuits such as processors, memory controllers, and memory devices typically include at least some digital circuitry that operates in response to a clock signal. Some integrated circuits may include some digital circuitry that operates in response to a first clock signal, and some digital circuitry that operates in response to a second clock signal. Different circuits that operate in response to different clock signals are said to be in different “clock domains.” Clock domains may be considered separate, or “disparate,” based on clock frequency differences, clock phase differences, locational differences, or the like. When circuits in various clock domains are powered up, link training may be performed to provide reliable communications between circuits in the different clock domains.
FIG. 1 shows a prior art system having integrated circuits with multiple clock domains. System 100 includes integrated circuits 110 and 150 interconnected by conductors 120 and 122. Integrated circuit 110 includes core circuit 112, input/output (I/O) circuit 114, and control circuit 116; and integrated circuit 150 includes core circuit 152, I/O circuit 154, and control circuit 156. Within integrated circuit 110, core circuit 112 and I/O circuit 114 are in different clock domains, and within integrated circuit 150, core circuit 152 and I/O circuit 154 are in different clock domains.
When power is supplied to system 100, the integrated circuits perform a link training operation to align clock and data signals between the core circuits and I/O circuits within the integrated circuits, and also on conductors 120 and 122 between the integrated circuits. For example, when power is applied, core circuit 112 may source training data that travels to I/O circuit 114, I/O circuit 154, core circuit 152, and then back. Likewise, core circuit 152 may source training data that travels to I/O circuit 154, I/O circuit 114, core circuit 112, and then back. Link training loops between the integrated circuits are formed to allow both integrated circuits to adjust both internal and external timing using their respective control circuits.